1. Field of the Invention
The present invention relates to an apparatus for polishing a semiconductor substrate and to a polishing method of a semiconductor substrate. More particularly, the present invention relates to a polishing solution supply system and to a method of supplying a polishing solution to the polishing apparatus.
2. Description of the Background Art
With downsizing of semiconductor integrated circuits, it has become essential to secure the flatness of interlayer insulation films. This is because the margin for the depth of focus in the photolithography processes contracts, or the margin for the quantity of over-etching in the etching processes contracts, unless the flatness of the interlayer insulation films is secured.
The following methods are given as method of flattening interlayer insulation films.
The first method is to form a BPSG (borophosphosilicate glass) film on a semiconductor substrate, and then the BPSG film is subjected to heat treatment to cause the viscous flow of the film so as to flatten the film.
The second method is to fill the depression formed on a substrate using SOG (spin on glass), and then to form an interlayer insulation film so as to flatten the film.
The third method is to apply a photoresist onto an interlayer insulation film, and to etch the photoresist and the interlayer insulation film in the same selection ratio so as to flatten the film.
The fourth method is to flatten the interlayer insulation film using the CMP (chemical mechanical polishing) method.
Further, various modifications by combining the above-described methods have also been proposed.
Next, with reference to FIGS. 9A to 9C, a conventional method of manufacturing a semiconductor device using the CMP method will be described.
First, a wiring layer (not shown) is formed on a semiconductor substrate 101.
Here, a dummy pattern is disposed of the wiring layer so as to match the occupancy ratio of patterns. However, due to various limitations of the device structure, the portions where distances between patterns are dense and sparse, i.e., sparse-dense difference, are produced in the wiring layer.
Next, an interlayer insulation film 102 is formed on the wiring layer having the above-described sparse-dense difference. Thus, the structure shown in FIG. 9A is obtained. That is, a small protruded portions 102a and a large protruded portions 102b are formed on the surface of the interlayer insulation film 102 corresponding to the undulations of the underlying wiring layer.
Next, as shown in FIG. 9B, abrasive slurry containing silica abrasive grains 104 is supplied between the semiconductor substrate 101 and a polishing table 105, and polishing is performed using the CMP method.
As a result, the structure shown in FIG. 9C is obtained. That is, although the small protruded portions 102a have been polished, the large protruded portions 102b, for example of the millimeter order, have not been polished, and the interlayer insulation film 102 has not been flattened. Furthermore, in large protruded portions 102b, difference in thickness occurs between the center portions and the edge portions.
FIG. 10 is a cross-sectional view for describing the stress distribution applied to the polishing stage. As shown in FIG. 10, the distribution of stress “A” applied to the polishing table 105 becomes uneven in the interlayer insulation film 102 having the undulations. This results in difference in the polishing rate, causing poor flatness (see FIG. 9).
Thus, there has been a problem that the dimension of the protruded portions to be polished (for example, the interlayer insulation film 102) cause difference in the degree of flatness. That is, CMP using the abrasive slurry containing silica abrasive grains 104 has pattern dependency.
As described above, for devices having sparse-dense difference in the object to be polished due to structural limitation, methods for improving flatness have been proposed, such as methods disclosed in the Japanese patent documents whose publication No. 11-145,140 and No. 9-246,219.
In these methods, as shown in FIG. 11, a film to be polished is made to have a dual-layer structure, and as the upper-layer film to be polished, a thin film having a low polishing rate is disposed.
Specifically, as shown in FIG. 11A, a first interlayer insulation film 102 is formed on a semiconductor substrate 101.
Next, as shown in FIG. 11B, a second interlayer insulation film 106 is formed on the first interlayer insulation film 102.
Then, as shown in FIG. 11C, abrasive slurry containing silica abrasive grains 104 is supplied between the semiconductor substrate 101 and the polishing table 105, and polishing is performed using the CMP method.
As a result, a structure shown in FIG. 11D is obtained. Namely, flatness of the interlayer insulation film is improved.
However, since the film to be polished has the dual-layer structure in the methods disclosed in Japanese patent documents whose publication No. 11-145,140 and No. 9-246,219 (see FIG. 11), the number of masks for exposure and the number of process steps increase.
Consequently, there is a problem that the time taken for the manufacture of semiconductor devices becomes much longer. Also, there is another problem that the manufacturing costs become much higher.
In addition to the above-described improvement in the design and the structure, that is, the method of improving flatness by making the film to be polished to have a dual-layer structure, slurry that has a highly flattening function (hereafter called “highly flattening slurry”) has been proposed in recent years.
Here, highly flattening slurry is conventional abrasive slurry, to which aqueous solution of organic acid or aqueous solution of hydrogen peroxide is added as additive.
However, the above-described highly flattening slurry has a problem that the abrasive slurry and the additive cannot be mixed well.
This is because abrasive grains coagulate when the additive is mixed with the abrasive slurry for preparing highly flattening slurry, and abrasive grains having a large particle diameter (hereafter called “coarse grains”) are formed.
FIG. 12 is a drawing for describing a change in the number of abrasive grains contained in polishing solution. FIG. 12 shows a change in the number of coarse grains having a particle diameter of 1.66 μm or larger. As shown in FIG. 12, the number of coarse grains shows about four times increase after mixing the additive for imparting the highly flattening function.
The coarse grains increased in above-described polishing solution mixing cause scratch (polishing scratch) formed on the semiconductor substrate to increase. This scratch has a problem to lower the product yield in semiconductor manufacturing processes.